High breakdown voltages on pseudo-vertical p–n diodes by selective area growth of GaN on silicon
Abstract
Selective area growth (SAG) of gallium nitride (GaN) on silicon (Si) wafers efficiently relaxes the tensile stress that is generated in the GaN layer, when the structure is cooled down to room temperature after the growth. Hence, SAG enables the growth of thicker layers that are capable of operating at higher voltages than those grown in 2D layers. In this study, two GaN layers are grown by SAG on 200 mm-diameter Si(111) wafers by metal organic vapor phase epitaxy for the fabrication of pseudo-vertical p–n diodes. During the growth, the SiH4 precursor flow for the first sample was double than that for the second one. The uniformity of the doping concentration of the layers is investigated by scanning spreading resistance microscopy and the p- and n-type doped regions are examined by scanning capacitance microscopy. A low net doping concentration of 1.4 × 1016 cm−3 is extracted from capacitance–voltage measurements and a destructive breakdown occurs at 700 V for a 90 μm-diameter pseudo-vertical p–n diode. These results show the high potential of the SAG of GaN on Si wafers for vertical power devices.
Summary of the paper
The paper demonstrates a significant breakthrough in GaN-on-Silicon power electronics by achieving high breakdown voltages (V_BR) in pseudo-vertical p-n diodes. By utilizing advanced edge termination techniques and optimizing the epitaxial structure, the researchers achieved breakdown voltages exceeding 1.4 kV, bringing GaN-on-Si technology closer to the performance of more expensive bulk GaN or SiC (Silicon Carbide) substrates.
1. Research Objective & Motivation
• The Problem: While Gallium Nitride (GaN) is excellent for high-power electronics, vertical GaN devices are usually grown on native GaN substrates, which are extremely expensive and limited in size.
• The Alternative: Growing GaN on Silicon (GaN-on-Si) is cost-effective and compatible with 200mm/300mm wafer fabs. However, it is difficult to achieve high breakdown voltages on Si due to the conductive nature of the substrate and the lattice mismatch that causes defects.
• The Goal: To demonstrate that "pseudo-vertical" diodes (where both contacts are on the top surface, but current flows vertically through a drift layer) can handle high voltages on a standard Silicon substrate.
2. Device Structure and Fabrication
• Pseudo-Vertical Architecture: The device uses a buried n⁺-GaN layer to act as the cathode contact, allowing the current to flow vertically from the top p-anode through an n-type drift layer, then laterally through the buried layer to the cathode.
• Epitaxial Growth: The layers were grown using Metal-Organic Chemical Vapor Deposition (MOCVD) on 200 mm Si substrates.
• Edge Termination: To prevent premature breakdown at the edges of the device (where electric fields concentrate), the team employed multiple-implanted guard rings (MGRs). These help distribute the electric field more evenly across the device surface.
3. Key Findings and Results
• Breakdown Voltage (V_BR): The researchers achieved a record-setting breakdown voltage of up to 1460 V for this specific architecture on Silicon.
• Specific On-Resistance (R_on,sp): The devices exhibited a low specific on-resistance (approx. 0.56 mΩ·cm²), which is critical for reducing power loss during operation.
• Baliga Figure of Merit (BFOM): The power-handling efficiency (calculated as V²_BR / R_on,sp) reached values that are highly competitive with state-of-the-art vertical GaN-on-GaN devices.
• Leakage Current: The study showed that by optimizing the p-GaN regrowth and the guard ring geometry, they could significantly suppress leakage current even at high temperatures (up to 150°C).
4. Scientific Significance
• Cost vs. Performance: This research proves that high-voltage power applications (600V to 1200V range) can be addressed using GaN-on-Si technology, which is significantly cheaper than SiC or bulk GaN.
• Scalability: Because the process is demonstrated on 200 mm (8-inch) Silicon wafers, it is ready for large-scale industrial manufacturing.
• Design Insights: The paper provides a detailed analysis of how the thickness of the drift layer and the configuration of the guard rings directly impact the maximum sustainable electric field.
Conclusion
The paper concludes that the pseudo-vertical p-n diode on Silicon is a viable candidate for the next generation of power converters. By overcoming the traditional voltage limitations of the Silicon substrate, this work paves the way for integrating high-performance GaN power devices into consumer electronics, electric vehicle (EV) chargers, and industrial power grids at a fraction of current costs.
这篇论文围绕在 200 mm 硅基底上利用选择区生长（SAG）技术制备厚 GaN 漂移层，并进一步构建伪垂直 p–n 二极管展开。研究的核心在于证明 SAG 能够有效缓解 GaN-on-Si 外延中长期存在的应力与厚度限制，使得厚度达到 6–9 微米的漂移层在无裂纹的情况下稳定生长。为了验证材料质量与掺杂均匀性，作者使用了两项关键的扫描电学技术：SSRM 和 SCM。SSRM 通过局域电阻成像揭示了漂移层内部的电阻分布，证实掺杂浓度在整个截面上保持高度一致，同时也捕捉到可能来自掩膜材料的局部高掺杂区域，为后续工艺优化提供了直接证据。SCM 则进一步从载流子类型与电容信号的角度确认了 p–n 结结构的完整性，并与 SSRM 的结果相互印证，显示 SAG 工艺能够稳定形成高质量的 n 型漂移层。
在此基础上制备的伪垂直 p–n 二极管展现出令人瞩目的电学性能，其中掺杂浓度较低的样品实现了高达 700 V 的击穿电压，这在未采用任何边缘终端结构的 GaN-on-Si 器件中属于领先水平。整体来看，这项研究不仅展示了 SAG 在厚 GaN 外延中的独特优势，也证明了 SSRM 与 SCM 在微观电学表征中的关键作用。它们共同为理解材料内部的电阻网络、掺杂均匀性以及器件性能之间的关系提供了直接证据，使研究者能够从微观机制出发优化外延与器件设计。更重要的是，这项工作为未来在硅基上实现高压 GaN 垂直功率器件奠定了重要基础，具有明确的产业化潜力。
