Van der Waals Ferroelectric CuCrP2S6-Enabled Hysteresis-Free Negative Capacitance Field-Effect Transistors
Han Chen, Yinfeng Long, Shiyu Zhang, Kai Liu, Mingfeng Chen, Jinxiu Zhao, Mengwei Si, and Lin Wang
Abstract
The relentless pursuit of miniaturization and reduced power consumption in information technology demands innovative device architectures. Negative capacitance field‐effect transistors (NC‐FETs) offer a promising solution by harnessing the negative capacitance effect of ferroelectric materials to amplify gate voltage and achieve steep subthreshold swings (SS). In this work, 2D van der Waals (vdW) ferroelectric CuCrP2S6 (CCPS) is employed as the gate dielectric to realize hysteresis‐free NC‐FETs technology. Scanning microwave impedance microscopy (sMIM) is employed to investigate the dielectric property of CCPS, revealing a thickness‐independent dielectric constant of ≈35. Subsequently, NC‐FETs are fabricated with MoS2 channel, and the capacitance matching conditions are meticulously investigated. The optimized devices exhibit simultaneously ultra‐steep SS (≈12 mV dec⁻¹) and negligible hysteresis, with immunity to both voltage scan range and scan rate. Finally, a resistor‐loaded inverter is demonstrated manifesting a low operation voltage down to 0.2 V and hysteresis‐free transfer characteristics. This work paves the way for the development of high‐performance, low‐power electronics by exploiting 2D vdW ferroelectric materials.
Summary of the paper
This study utilizes 2D van der Waals (vdW) ferroelectric CuCrP2S6 (CCPS) as the gate dielectric to develop hysteresis-free negative capacitance field-effect transistors (NC-FETs) for low-power electronics.
Key findings include:
Scanning Microwave Impedance Microscopy (sMIM) characterizes CCPS’s dielectric properties, revealing a thickness-independent dielectric constant (~35) across 6–70 nm, validated by finite element analysis (FEA) and capacitance-voltage (C-V) measurements.
Optimized NC-FETs with MoS2 channels (via precise capacitance matching between CCPS and MoS2) exhibit ultra-steep subthreshold swing (~12 mV/dec), negligible hysteresis (insensitive to voltage scan range/rate), and high on-off ratio (~10⁶).
A resistor-loaded inverter based on the NC-FET operates at a low supply voltage (0.2 V) with ultralow power consumption (1.67 pW) and maintains a voltage gain >1, meeting low-power logic circuit requirements.
This work highlights CCPS' s potential for advancing high-performance, low-power post-Moore NC-FET technologies.
在本篇文章中，扫描微波阻抗显微镜SMIM具体的应用场景和作用如下：
- 表征CCPS的介电特性：通过 sMIM 技术结合有限元模拟（FEA），定量测定范德华铁电材料CuCrP₂S₆（CCPS）的相对介电常数，发现其在 6-70 nm 厚度范围内呈厚度无关性，数值稳定在≈35，且该结果与电容 - 电压（C-V）测量一致，为后续器件电容匹配设计提供关键参数。
- 获取CCPS厚度 - 信号关系：通过sMIM成像提取CCPS纳米片与Au衬底的信号对比度，观察到信号与厚度呈准反比关系，进一步辅助介电常数的定量分析，明确CCPS作为栅极介电材料的厚度适配范围。
- 支撑NC-FET器件设计：基于sMIM测得的CCPS介电常数（≈35），结合 MoS₂的介电常数（≈7），推导得出CCPS与MoS₂的厚度匹配条件（T_CCPS ≤ (T_MoS₂・ε_CCPS)/ε_MoS₂），为优化NC-FET器件结构、实现无滞后特性和超陡亚阈值摆幅（≈12 mV/dec）提供数据支撑。
